This invention relates to the fabrication of an integrated circuit structure in which silicidation is selectively performed within individual integrated circuit structures to reduce current leakage.
Today, our society is heavily dependent on high-tech electronic devices for everyday activity. Integrated circuits are the components that give life to our electronic devices. Integrated circuits, including memory components and logic components, are found in widespread use throughout the world, in appliances, in televisions and personal computers, and even in automobiles. Additionally, modern manufacturing and production facilities are becoming increasingly dependent on the use of machines controlled by integrated circuits for operational and production efficiencies. Indeed, in many ways, our everyday life could not function as it does without integrated circuits. These integrated circuits are manufactured in huge quantities in our country and abroad. Improved integrated circuit manufacturing processes have led to drastic price reductions and performance enhancements for these devices. Examples of performance enhancements include faster processing speeds and reduced power usage.
The traditional integrated circuit memory cell fabrication process begins with a wafer of silicon and involves four basic operations: 1) layering, 2) patterning, 3) doping, and 4) heat treatment. Layering is the process of depositing materials which have different conductive characteristics such as insulators or conductors in layers on the silicon wafer until the devices are complete. These layers of material can be deposited in geometric patterns so that materials with different conductive characteristics are stacked on top of each other to create an operational integrated circuit in three dimensions. The patterning process used to fabricate integrated circuits is typically performed using lithography followed by a variety of subtractive (etch) and additive (deposition) processes. Doping can be used to create areas of P type (hole-mobile) silicon or N type (electron-mobile) silicon. Complementary metal-oxide-semiconductors (CMOS) are composed of complementary P type and N type Field Effect Transistors (PFETs and NFETS). Heat treatment can be used to activate dopants and repair damage in wafers (annealing) or to provide electrical connections between metal layers and silicon layers (alloying). These fabrication methods are well known in the art.
One process regularly used in the fabrication of semiconductor structures is silicidation. Silicidation is a process by which a conductive layer of metal-silicon alloy is formed in an integrated circuit structure. Usually, silicidation occurs by blanketing a layer of metal, most commonly titanium or cobalt, across an entire wafer surface and heat-treating the surface to form a conductive metal-silicon compound wherever silicon is exposed. Metal-silicon alloys such as titanium disilicide (TiSi2) or cobalt disilicide (CoSi2) can be formed at the areas of exposed silicon. Silicidation is desirable in semiconductor structures in many instances because the application of this conductive layer reduces the resistance in silicon active regions, especially in polysilicon lines. This reduction in resistance will reduce the amount of time that it takes for a signal to travel through the chip or the integrated circuit, will reduce the voltage at which a chip can operate, and will improve the chip""s performance.
While silicidation may reduce resistance between elements, allowing the elements to operate more effectively, this same process of silicidation may also exacerbate current leakage. Current leakage increases power usage and reduces battery life. While competitive forces demand the improved performance associated with silicidation, those same competitive forces also demand reductions in power usage of integrated circuits. Reduced power usage leads to highly desirable longer battery life for devices such as portable computers, cellular telephones, and other portable devices.
Therefore, there exists a need to improve the performance of integrated circuits or chips while at the same time reducing power usage of the circuit.
In a first aspect, the invention comprises a semiconductor structure comprising an N+ diffusion and a P+ diffusion formed in a semiconductor substrate; a polysilicon line formed on the substrate intersecting the N+ diffusion and the P+ diffusion; wherein the polysilicon line has a P+ region, an N+ region and an N+/P+ junction area therebetween; a silicide strap extending across the N+/P+ junction area of the polysilicon line wherein the suicide strap forms an electrical connection between the P+ region of the polysilicon line and the N+ region of the polysilicon line; and wherein the N+ diffusion or the P+ diffusion are not silicided.
In a second aspect, the invention comprises a method for forming a semiconductor apparatus comprising the steps of forming an N+ diffusion and a P+ diffusion; forming a polysilicon line, the polysilicon line having a P+ region and an N+ region, the polysilicon line having an N+/P+ junction area wherein said junction area comprises the area where the P+ region of the polysilicon line and the N+region of the polysilicon line abut each other; and, selectively forming a silicide strap extending across the junction area, wherein the silicide strap forms an electrical connection between the P+ region of the polysilicon line and the N+ region of the polysilicon line; and selectively preventing the formation of silicide on the N+ diffusion and the P+ diffusion.
In the invention, by selectively applying silicide at the N+/P+ junction, a low resistance connection can be made between the N+ and P+ regions of the polysilicon line, which increases the conductivity in this region. By selectively not applying silicide over the NFET and PFET regions, the current leakage that occurs as a result of blanket silicidation is minimized.
The foregoing and other features and advantages of the invention will be apparent from the following more particular description of preferred embodiments of the invention, as illustrated in the accompanying drawings.